1. Field of the Invention
The present invention relates to a memory circuit in which a memory cell array having a plurality of memory cells is used as a look-up table for a logic function, and particularly relates to a memory circuit configured to be capable of selectively reading from a plurality of look-up tables, and read control method thereof.
2. Description of the Related Art
In recent years, in order to use LSI for various purposes, techniques for allowing users to freely change the configuration of the LSI has been achieved. For example, a programmable logic LSI is configured, in which a large number of logic circuits are arranged, logic functions and connection relations are set according to configuration data, and it is possible to achieve various logic functions by changing the configuration data. Generally when achieving a function of the logic circuit, a look-up table (LUT) corresponding to a desired logic function is configured in a memory, and thereby an arbitrary logic function capable of externally outputting a logic output signal having a predetermined number of bits corresponding to a logic input signal having a predetermined number of bits can be implemented.
In order to achieve a complex logic function, a configuration is proposed in which LUTs corresponding to a large scale logic function having many inputs and outputs are configured in a memory circuit so as to connect the LUTs in cascade (see Japanese Patent Laid-Open No. 2004-258799). By accessing the memory circuit configured in this manner many times with an input variable being changed, the large scale logic function can be achieved.
However, according to the above conventional configuration of the LUT, when implementing a logic function having extremely large scale, the number of bits of a logic input signal serving as the input variable is increased in addition to an increase in capacity of the memory circuit. As a result, the number of decode signals generated based on the logic input signal in order to select data to be accessed in the LUT is rapidly increased. For example, when implementing an n-input logic function, 2n decode signals are required. Accordingly, when the LUT is configured in the memory circuit, its circuit scale is increased and an area for arranging a large number of lines is required.
Further, according to the above conventional configuration of the LUT, control for accessing a plurality of LUTs is not assumed, a problem arises in that latency when obtaining an output logic signal of the LUT is increased. Particularly, when the plurality of LUTs is configured in a memory circuit operating in a low speed, a reduction in throughput due to accumulation of latencies becomes a serious problem.